1. Field of the Invention
The present invention relates in general to fast carry transfer apparatus, and more particularly to a carry transfer apparatus in which a reduced number of transistors are used to reduce a layout area of a chip and a transfer delay time of a carry signal in designing a logic circuit.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a detailed circuit diagram of a conventional carry transfer apparatus. As shown in this drawing, the conventional carry transfer apparatus comprises first to fourth groups 10-40, inverters I1-I6 and NMOS transistors MN1-MN2.
The first group 10 comprises NMOS transistors MN13 and MN14. The NMOS transistor MN13 has a gate connected to a first signal input terminal S4b and a drain connected to a second signal input terminal C4b. Similarly, the NMOS transistor MN14 has a gate connected to the first signal input terminal S4b and a drain connected to the second signal input terminal C4b.
Also, the first group 10 comprises an exclusive-NOR gate EXR11 having one input terminal connected to the first signal input terminal S4b, an inverter I11 having an input terminal connected to the first signal input terminal S4b, and NMOS transistors MN11 and MN12.
The NMOS transistor MN11 has a gate connected to an output terminal of the inverter I11, a source connected to a source of the NMOS transistor MN13 and a drain connected to a power source voltage terminal V.sub.DD. The NMOS transistor MN12 has a gate connected to the output terminal of the inverter I11, a source connected to a source of the NMOS transistor MN14 and a drain connected to a ground voltage terminal GND.
The first group 10 also comprises an inverter I12 having an input terminal connected to the power source voltage terminal V.sub.DD, an inverter I13 having an input terminal connected to the ground voltage terminal GND, and NMOS transistors MN15 and MN16.
The NMOS transistor MN15 has a drain connected to an output terminal of the inverter I12 and a source connected to the other input terminal of the exclusive-NOR gate EXR11. The NMOS transistor MN16 has a drain connected to an output terminal of the inverter I13 and a source connected to the other input terminal of the exclusive-NOR gate EXR11.
In the same manner as those of the first group 10, the second to fourth groups 20-40 have NMOS transistors MN21-MN26, MN31-MN36 and MN41-MN46, inverters I21-I23, I31-I33 and I41- I43 and exclusive-NOR gates EXR21, EXR31 and EXR41, respectively, associated with first signal input terminals S5b-S7b and second signal input terminals C5b-C7b.
The inverters I1 and I2 are connected in series to a carry signal input terminal C1. An output terminal of the inverter I2 is connected to gates of the NMOS transistors MN15, MN25, MN35 and MN45 in the first to fourth groups 10-40 and a gate of the NMOS transistor MN1. An output terminal of the inverter I1 is connected to gates of the NMOS transistors MN16, MN26, MN36 and MN46 in the first to fourth groups 10-40 and a gate of the NMOS transistor MN2.
As mentioned above, the drain of the NMOS transistor MN11 in the first group 10 is connected to the power source voltage terminal V.sub.DD. The source of the NMOS transistor MN11 in the first group 10 is connected to drains of the NMOS transistors MN21, MN31 and MN41 in the second to fourth groups 20-40. The inverters I3 and I4 are connected in series to a source of the NMOS transistor MN41 in the fourth group 40. An output terminal of the inverter I4 is connected to a drain of the NMOS transistor MN1.
Also, the drain of the NMOS transistor MN12 in the first group 10 is connected to the ground voltage terminal GND. The source of the NMOS transistor MN12 in the first group 10 is connected to drains of the NMOS transistors MN22, MN32 and MN42 in the second to fourth groups 20-40. The inverters I5 and I6 are connected in series to a source of the NMOS transistor MN42 in the fourth group 40. An output terminal of the inverter I6 is connected to a drain of the NMOS transistor MN2. Sources of the NMOS transistors MN1 and MN2 are connected in common. A common connection point of the sources of the NMOS transistors MN1 and MN2 is connected to a carry signal output terminal C2.
The operation of the conventional carry transfer apparatus with the above-mentioned construction will hereinafter be described.
First, if the carry signal C1 is logically low, an output signal from the inverter I1 is logically high and an output signal from the inverter I2 is logically low.
The low output signal from the inverter I2 turns off the NMOS transistor MN15 in the first group 10, whereas the high output signal from the inverter I1 turns on the NMOS transistor MN16 in the first group 10. As a result, the NMOS transistors MN12 and MN14 in the first group 10 are turned on.
On the contrary, if the carry signal C1 is logically high, the output signal from the inverter I1 is logically low and the output signal from the inverter I2 is logically high.
The high output signal from the inverter I2 turns on the NMOS transistor MN15 in the first group 10, whereas the low output signal from the inverter I1 turns off the NMOS transistor MN16 in the first group 10. As a result, the NMOS transistors MN11 and MN13 in the first group 10 are turned on.
With the above operation performed, the final signals S4-S7 are outputted by summing the first input signals S4b-S7b with the carry signal C1. At this time, the second input signals C4b-C7b are outputted as the carry signal C2 when all of them are logically high.
In the case where all the first input signals S4b-S7b are logically low and all the second input signals C4b-C7b are logically low, the carry signal C1 is not transferred to the next stage, thereby causing the carry signal C2 to become logically low. Also, in the case where all the first input signals S4b-S7b are logically high and all the second input signals C4b-C7b are logically low, the carry signal C1 is transferred to the next stage. In this case, the carry signal C1 is outputted as the carry signal C2.
Namely, upon receiving the first and second input signals S4b-S7b and C4b-C7b, the groups 10-40 perform carry operations of the first and second input signals S4b-S7b and C4b-C7b. Therefore, a transfer speed of the input signals C4b-C7b and the carry signal C1 becomes fast.
At this time, a transfer delay time of the carry signal C1 is determined by summing a transfer time of the carry signal C1 based on the power source voltage V.sub.DD and the ground voltage GND and a switching time of the NMOS transistors MN1 and MN2.
However, the above-mentioned conventional carry transfer apparatus has a disadvantage in that the transistors used in each group are large in number, resulting in an increase in a layout area of a chip and an increase in the transfer delay time of the carry signal in designing a logic circuit.